`timescale 1ns / 1ps

module bits_8(//control gnd port
    input [1:0] f,
    input [3:0] bit1,
    input [3:0] bit2,
    input [3:0] bit4,
    input [3:0] bit5,
    input [3:0] bit7,
    input [3:0] bit8,
    output [23:0] bit_out
    );
    reg [3:0] dig_r1;
    reg [3:0] dig_r2;
    reg [7:0] gnd;
    always @ (f) begin
        case (f)
            2'b00: begin
                dig_r1 <= bit1;
                dig_r2 <= bit5;
                gnd <= 8'b10001000;//light on bit1 & bit5
            end
            2'b01: begin
                dig_r1 <= bit2;
                dig_r2 <= 4'd10;
                gnd <= 8'b01000100;//light on bit2 & bit6
            end
            2'b10: begin
                dig_r1 <= 4'd10;
                dig_r2 <= bit7;
                gnd <= 8'b00100010;//light on bit3 & bit7
            end
            2'b11: begin
                dig_r1 <= bit4;
                dig_r2 <= bit8;
                gnd <= 8'b00010001;//light on bit4 & bit8
            end
        endcase
    end
    bit u1(.digit(dig_r1),.a(bit_out[0]),.b(bit_out[1]),.c(bit_out[2]),.d(bit_out[3]),.e(bit_out[4]),.f(bit_out[5]),.g(bit_out[6]),.dot(bit_out[7]));
    bit u2(.digit(dig_r2),.a(bit_out[8]),.b(bit_out[9]),.c(bit_out[10]),.d(bit_out[11]),.e(bit_out[12]),.f(bit_out[13]),.g(bit_out[14]),.dot(bit_out[15]));
    assign {bit_out[16],bit_out[17],bit_out[18],bit_out[19],bit_out[20],bit_out[21],bit_out[22],bit_out[23]} = gnd[7:0];
endmodule
